1. Field Embodiment
The embodiment relates to a program for estimating the peak of power consumption of an LSI, and a device for such a program. The embodiment particularly relates to a power consumption peak estimation program capable of estimating the peak of power consumption with a small number of man-hours, and a device for such a program.
2. Description of the Related Art
The design of a semiconductor integrated circuit (LSI) has the steps of logically synthesizing a RTL file written in a hardware description language (HDL) to create a netlist, and designing a layout based on this netlist to create layout data. In the stage of creating a netlist, logic verification and estimation of power consumption are performed.
As a tool for analyzing power consumption of an LSI, there is known the PrimePower (product name) manufactured by Synopsys, Inc. This power consumption analysis tool takes signal waveform data of a circuit cell as input data, the signal waveform data being obtained by performing a logic simulation on a netlist, and calculates power consumption in a predetermined time period from the signal waveform data and power consumption data of a cell within a cell library. By calculating power consumption from the signal waveform data for every clock cycle, a peak value of the power consumption in the predetermined time period can be estimated.
Japanese Patent Application Laid-Open No. 2004-62238, Japanese Patent Application Laid-Open No. 2002-288257, Japanese Patent Application Laid-Open No. 2001-59856, Japanese Patent Application Laid-Open No. 2003-256495, and Japanese Patent Application Laid-Open No. H2-136755 describe a method of estimating power consumption of an LSI.
According to Japanese Patent Application Laid-Open No. 2004-62238, a measurement circuit for measuring a signal variable of a gate is added to a target logic circuit in which power consumption in a integrated circuit is to be calculated, to configure a device, and signal variables measured after a certain operation are accumulated, whereby power consumption in a logic circuit is calculated.
According to Japanese Patent Application Laid-Open No. 2002-288257, a toggle detection circuit aspects a toggle of a logic gate output of a target circuit for power consumption measurement and adds up the number of toggles, and the number of toggles of the toggle detection circuit is extracted at the end of simulation to calculate power consumption.
Japanese Patent Application Laid-Open No. 2001-59856 describes a structure, test method and design method for restraining peak power consumption at the time of testing an integrated circuit device.
According to Japanese Patent Application Laid-Open No. 2003-256495, logic circuit simulation is executed using a RT netlist and test pattern of the entire LSI to collect the number of memory accesses, while simulation is executed using a netlist of a memory section to collect memory consumption current, and memory average power consumption is calculated from the number of memory accesses and the memory consumption current.
According to Japanese Patent Application Laid-Open No. H2-136755, logic simulation is executed on a digital circuit to obtain digital operation historical information of each element, and the total consumption current of a target circuit for consumption current estimation is estimated based on the digital operation historical information and a general formula for consumption current estimation for each element. Japanese Patent Application Laid-Open No. H2-171861 describes the same thing as Japanese Patent Application Laid-Open No. H2-136755, regarding the method of calculating the power consumption of a CMOS gate array.
On the other hand, Japanese Patent Application Laid-Open No. 2002-92065 describes a circuit design method for selectively changing a flip-flop to a flip-flop having a gated flip-flop buffer, in order to cut power consumption of an LSI.
Recently LSI's have been miniaturized and subjected to power/voltage reduction, thus the voltage drop caused by extreme power consumption has been a problem. Therefore, it is required to estimate, in a stage of developing an LSI, the detail of the processing of the LSI in which the peak of power consumption is generated, the time at which the processing occurs, as well as peak values.
In a conventional power analysis method, logic simulation is executed to obtain signal waveform data of a cell, and then power consumption for every cycle is obtained based on the signal waveform data and the power consumption data of a cell library, as described above. A power consumption peak can be obtained from the obtained power consumption in each cycle.
However, it is difficult to predict the operation in which the power consumption of an LSI reaches a peak value. Therefore, logical simulation cannot performed in a limited manner only on a time period having the peak value. For this reason, it is necessary to execute logic simulation on all operations that the LSI might perform, requiring long hours of logic simulation. Such logic simulation means to realize the same operation as a state in which the system is actually applied, and usually has tens of million through hundreds of millions of cycles.
In the long hours of logic simulation, it takes several weeks to several months to extract the signal waveform data of a long cycle in a simulation using a software simulator, which is not realistic. Further, even when performing simulation using hardware such as an emulator, large amounts of signal waveform data have to be transferred to a host computer, requiring a long period of time.
In conventional power consumption peak estimation programs for an LSI take a large number of man-hours to estimate the power consumption.